1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to spacers adjacent to sidewalls of the gate. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate. After the source and drain are doped, the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
Photolithography is frequently used to create patterns that define where the polysilicon layer is etched. Typically, the wafer is cleaned and prebaked to drive off moisture and promote adhesion, an adhesion promoter is deposited on the wafer, a few milliliters of positive photoresist are deposited onto the spinning wafer to provide a uniform layer, the photoresist is soft baked to drive off excess solvents, the photoresist is irradiated with an image pattern that renders selected portions of the photoresist soluble, a developer removes the irradiated portions of the photoresist, an optional de-scum removes very small quantities of photoresist in unwanted areas, the photoresist is hard baked to remove residual solvents and improve adhesion and etch resistance, the etch is applied using the photoresist as an etch mask, and the photoresist is stripped. Therefore, the photoresist has the primary functions of replicating the image pattern and protecting the underlying polysilicon when etching occurs.
Increasing the photoresist thickness generally decreases the accuracy in which the photoresist replicates the image pattern. For instance, variations in photoresist thickness can result in changes in photoresist linewidth, and increasing the photoresist thickness often leads to larger variations in the photoresist thickness. Furthermore, the image pattern generates standing waves caused by actinic light waves that propagate through the photoresist down to the polysilicon and reflect off the polysilicon back through the photoresist. The reflected waves constructively and destructively interfere with the incident waves to create zones of high and low exposure with a separation of (.lambda./4n), where .lambda. is the wavelength of the image pattern and n is the index of refraction of the photoresist. Standing waves are disadvantageous because the periodic variation of light intensity in the photoresist causes the photoresist to receive nonuniform doses of energy through the layer thickness. Increasing the photoresist thickness tends to increase the problems associated with standing waves.
Although the photoresist is eroded by the etch, the photoresist must be thick enough to avoid being removed by the etch. The minimum thickness of the photoresist depends on the selectivity of the etch with respect to the photoresist, the selectivity of the etch with respect to the polysilicon, and the thickness of the polysilicon. In general, the etch is highly anisotropic and forms the gate with vertical sidewalls since tapered sidewalls might affect the channel length. In addition, the etch is highly selective of polysilicon with respect to the underlying silicon dioxide. To meet these requirements, the etch typically utilizes etch gases containing both chlorine (such as Cl.sub.2) and fluorine (such as SF.sub.6). As a result, the photoresist is often on the order of 4 times as thick as the underlying polysilicon to assure that the etch does not remove the photoresist.
For submicron geometries, the gate thickness is usually on the order of 2000 to 2500 angstroms so that the gate provides an implant mask for the underlying channel region during ion implantation of the source and drain. Therefore, the photoresist that defines the gate needs a thickness on the order of 8000 to 10,000 angstroms. Unfortunately, at such thickness, the photoresist may not accurately replicate the image pattern due to variations in photoresist thickness, standing waves and the like. Moreover, variations in photoresist linewidth can lead to variations in gate length (the critical dimension), which in turn can lead to variations in channel length and ultimately device performance.
Accordingly, a need exists for an improved method of making an IGFET that includes photolithography yet reduces unwanted variations in channel length and device performance.